1. Field of the Invention
The present invention relates to a static semiconductor memory device that allows simultaneous writing of data into memory cells connected to a plurality of selected word lines.
2. Description of the Background Art
As semiconductor memory devices having a high capacity for data storage, SRAMs (Static Random Access Memories), DRAMs (Dynamic Random Access Memories) and others have been put into practical use.
The semiconductor memory devices are shipped after determining pass/fail. The determination of pass/fail is performed by actually inputting and outputting data to and from memory cells included in the semiconductor memory device, and thereby determining whether written and read data matches with each other or not, or by applying a stress thereto by burn-in.
In recent years, the capacity of semiconductor memory devices has been increasing so that portions to be subjected to stresses in the semiconductor memory device have been increasing in number. This increases a test time for the burn-in, and thus causes a problem of a high cost. For overcoming this problem, Japanese Patent Laying-Open No. 04-232693 has disclosed a static semiconductor memory device including a word line drive circuit that is controlled to select and drive simultaneously all word lines in a voltage stress test, and a bit line load circuit that is controlled not to apply a bias potential to at least one of paired bit lines or to apply the bias potential lower than that in a normal operation to the bit line pair in the voltage stress test.
For applying a stress to the memory cell, it is preferable to set the memory cell to the write state by setting the potential of the word line to an H-level such that a maximum potential difference may be exerted on the bit lines and the storage nodes in the memory cell. For simultaneously applying the stress to many memory cells, it is effective to raise simultaneously many word lines and thereby to set the memory cells connected to each word line to the write state.
The stress applying method described above is practically available in DRAMs. However, when it is attempted in a full CMOS (Complementary Metal Oxide Semiconductor) SRAM to apply the stress to memory cells by simultaneously raising many word lines and performing the write operation, a balance is not kept between a total of current capabilities of load P-channel MOS transistors included in each memory cell and current capabilities of N-channel MOS transistors included in a write driver. In the full CMOS-SRAM, therefore, it becomes difficult to perform the simultaneous writing into the plurality of memory cells. This is because the size of the ordinary write driver is determined based on the assumption that the ordinary write driver performs the writing on one of the memory cells on one bit line pair. When the size of the write driver is determined to allow simultaneous writing into, e.g., 100 or more memory cells, this results in a problem that an area penalty becomes excessively large.
When the write state continues without changing information stored in the memory cell, a through-current flows in a CMOS inverter circuit forming the memory cell, and causes a problem that a large current flows through the whole semiconductor memory device.